Scheduling Workflow Applications on Processors with Different Netlib Netlib Form

Instructions and help about Scheduling Workflow Applications On Processors With Different Netlib Netlib

Hello, I am Cyril Six a PhD student. I'm  supervised by Sylvain Boulmé and David Monniaux.   We are from the Verimag laboratory which  is specialized in code verification   and I also work at the Kalray company  which produces and designs processors   in France. In this talk I will present how to  introduce instruction scheduling optimization   in a certified compiler such as CompCert  and I will present how that affects   interlocked VLIW processors such  as the one we are working on. To introduce instruction scheduling here is a  very simple piece of code. A piece of code does   an addition, a load from memory, and then a  subtraction using the value we just loaded.   Each instruction on the CPU takes a certain  amount of cycles which we call latency.   Here we are going to assume that the addition  and the subtraction have a latency of 1   while the load has a latency of 2. We are going  to execute that code through a simple processor   model pipeline