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Using Clock Jitter Analysis to Reduce BER in Serial Data Applications This Application Note Emphasizes on the Emerging Techniqu Form

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Vlsi data conversion circuits lecture 35 in the last class we were discussing the effects of clock jitter on the performance of a delta-sigma data converter loop and we saw that clock jitter affects both the sampling instant of the A to D converter as well as the the time at which the output of the DTA converter changes value and we were discussing specifically the NRC DAC and what we found was that even though the sampling instant of the ATD converter is altered the error does induced does not rEvally matter as far as the closed loop is concerned since these are this error occurs in parallel with the quantization noise which as we know is shaped out there for the jitter affecting the ATD converters not rEvally a concern on the other hand back Teeter adds directly at the input and is therefore detrimental to the SNR that one would otherwise obtain so in the last class we said that the effect of jitter is equivalent to an error sequence the output of the modulator which is delta T n by

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Using Clock Jitter Analysis to Reduce BER in Serial Data Applications This Application Note Emphasizes on the Emerging Techniqu Form

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