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all right good afternoon everybody great to see the the room with all these interested people in vector technology I'm Mark Ronson I work in the product team at sy5 specifically on the core IP risk 5 compatible product lines and we called this the sci-fi vector processor presentation I'm actually going to be talking about our vector processor roadmap and software development activities and I think and hope that you'll find it very interesting so alright so first of all scifi has been heavily involved and is investing in making the the vector extensions and vector technology within the RISC 5 community a reality and successful it's interesting that you know the inventors of RISC five were driven by the desire to have an open architecture that could be used for computer research and one of the key areas was actually vector research and now we've you know as as risk 5 is gained momentum and is plowing forward the vector extensions to that base architecture are being fully put in place so I wanted to talk about just for a moment about the fact that the the Sai 5 team is actually contributing to helping build out not only the ice itself where Krista's chairing the the vector extensions working group and driving the spec collaboratively within the community but also to point out that I you know we've developed the vector extensions to the assembler and to the spike instruction set simulator model we did those actually as internal projects at sci-fi band then contributed them that to the open source community so we're very motivated and excited to try to bring this to reality and we believe 2020 is the year that that all converges on solutions and part of that is actually building commercial solutions based on the underlying technology and that really leads to our site 5 intelligence processor line so what is a sci-fi of intelligence processor well really in the plural it's a portfolio of risk 5 core IP with vector intelligence and that starts with support for the risk 5 vector extensions this is being defined in a way to be highly scalable both in software and hardware so it's really not meant to be you know I'm implementing at a very high end processor or just a small extension for very entry-level processors it's really meant to scale and and that scalability comes with binary compatibility it also delivers on being able to develop complete solutions for scalar and vector processing within a single development environment so the second aspect of the intelligence processors is that we've got a 20/20 portfolio extending from microcontrollers up to robust application processor footprint solutions coming out I'll talk a little bit more about those shortly but the third aspect is and I I sort of touched on it but really we think the whole scalability the architecture aligns very well with some of Syfy's fundamental advantages and capabilities and how we build processor technology you have scalability and software and we marry that with our microarchitecture development to provide highly scalable configurable solutions so so this is our roadmap for the the vector intelligence processors it is loosely temporal as in going from left to right it follows time and and it covers a variety of footprints in terms of where it provides solutions across a very wide range of vector applicable technologies from IOT applications all the way up to the data center so the first product and the only one that I'm really going to touch on any additional layer of detail today is the the VI 2 Series core and just to give you a taster for today it's you know it actually is very extensible and applicable to a variety of markets as an initial focus we've been developing solutions really targeted for the the smart voice and audio market space and but it's applicable for general DSP applications and many many other applications beyond that as such it has element data type support common to DSP AI and general compute applications which essentially is integer fixed and floating point data types from 8 to 32 bit widths the as you would expect it builds on the the risk v vector extensions and it's really again it's leveraging that scalability that's built into the architecture to deliver that perform of what a vector compute engine can do we actually incorporate separate data paths for the scalar pipeline and the instruction pipeline the the initial default configuration and I'm telling you this today because we have some initial performance points that I'll share are it's basically a hundred and twenty eight bit wide data path with a 512 bit vector lengths per per register in a 32 register architecture and using elmo you can actually extend that to working on vectors as long as 4096 bits but again need to stress it's configurable ultimately and so the the points that I'm talking about there are for a specific initial default configuration and you know you can build you can build technology but you also need to be able to evaluate how your codes doing and debug it and and and trace it and this solution actually plays directly into our existing debug and trace hardware solutions so it can work easily with with our third-party tool offerings and worrying talking with and some of those vendors already in support of this and within our own freedom studio tools I you know things like visibility into the vector registers and control registers are part of the solution okay so let's let's talk a couple slides on performance so and I'll talk about this next aspect a little bit more a few slides later but we've actually developed a DSP library with vector support for that support the RISC v vector extensions this gives a a mapping at a at a loose level in terms of bucket izing the different functions across different operations in in the library the the net of it is all of this is being measured on 32-bit floating-point data types and and we see greater than a 9x speed-up I across the suite of DSP functions there and this is actually done on very small data sets I would consider this probably a conservative view of what you can see if you scale up the data set size further oh and just for full disclosure this is comparing vectorize assembly versus scaler source compiled to the the cpu so more specifically matrix multiplies are a big part of many application spaces including the whole AI and neural networking arena using that same library 32-bit floating-point workloads in this particular point and doing matrix multiply on a 256 element so 16 by 16 arrays multiplied together we see better than 20 2x performance scaling between the vector extensions and the scalar associated scalar performance and you can see you don't need to read it today but but basically you've got the scalar C code on the left and and the vectorized assembly on the right and this is actually with the scalar code unrolled without the unrolling and that obviously you know when you enroll code you expand the code size I believe the the the code size increased between these two scenario was about 2 or 3 X so it was pretty dramatic we when you don't unroll the code it's closer it's another 10x faster on the vector core so very significant difference and really those couple examples lead me to what I I think you may find interesting because we've not only been developing hardware but we've been investing heavily in the software side and our vector evaluation platform is really our our first vehicle for enabling the algorithmic evaluation and porting efforts with with the community and with customers and partners who want to test and evaluate their algorithms on the risk by vector extensions so it's actually comprised of a number of key tools and elements one area is the tool chain itself and that's a vectorized assembly or assembler but it also includes a GCC compiler and intrinsics that sy5 has developed for vector support to complement that I showed you a couple examples from the DSP library there's a there's a DSP optimized DSP library we wrote this with the idea of being compatible with the census DSP a is for those people utilizing those api's and software model it should ease ability to pull in use of the vector extensions and and then in select cases and we will continue to add to this we've done even more highly optimized FFT kernels and matrix math kernels so we're spending a lot of time on the software side not just on the hardware side and two as targets we support both a performance model and the spike instruction set simulator golden reference model for the the risk 5 community for for actually running the software key is it's actually available now so please contact us if you're interested in getting access to this platform I'm not going to go through lines of code here the point I really wanted to show is I made the claim on the last slide that we've developed vector intrinsics support and this just gives you a quick snapshot of an example vector addition implementation using the intrinsics on the left obviously the pound include statement are the intrinsics and then the actual intrinsic statements are are embedded in the code color coded and and the corresponding generate assembly on the right so i only had 20 minutes to talk to you today about this topic but I did want to summarize a few key takeaways from the talk and then give you a few minutes for any questions that you might have the first is I just want to reiterate I think you know the vector technology within the RISC 5 community is is becoming real it is 2020 as the year of the vector for the RISC 5 and we have big plans to not only make that a reality but also to invest and make it successful part of that investment and and reality is our delivering on a roadmap of sy 5 intelligence processors cutting a covering a wide range of implementation points and use cases are focused on investing in not only hardware but also software to enable solutions around the the vector extensions and really first first snapshot of that is is our introduction of the SyFy vector evaluation platform which is here to enable evaluation and porting and development of for hardware and software around vector technology and that's really that's really my last point it's a call to action software partners algorithm developers whether you're sitting here today are looking at my presentation later please contact sy5 to help vectorize your solutions for risk 5 and with that I thank you very much and I open up the room for questions yes the question was are we implementing the full vector specification it so depends if you're talking core or you know the the portfolio but the top-level answer is over over time yes the as an example on the the VI 2 core however I mentioned the data types that are supported we're not supporting double precision floating point and initially working with customers we we have made some choices but over the the medium term the answer is generally yes target frequency so yeah so the question was is there a target frequency that's again that's a very core dependent question we'll be revealing more details about each of the individual cores as we fully announce them in 2020 but I guess as a general statement I can say that on the Durham enough the VI to core that I showed today we do not see it being appreciably slower than the existing two series lineup in the sci-fi portfolio yes I think I heard the question the question was I will we have open blasts support for the the Sai v vector course I think high probability yes probably even more than high probability yes I'm not going to give a specific timeline today but but next year is probably a good guess I very sorry question was very much a microarchitecture question how many core or how many vector instructions can be dispatched per cycle in our course and will reveal those details on a core bike core basis but the the VI two core that I showed one layer of detail when you see separate data paths and and things like that it should you know generally we're implementing several execution engines for different parameters so the actual instruction fetch decode issue aspect is is common but beyond that you can see a lot of parallelism in execution yes especially across the the range that I was showing today yeah yeah so I'm I'm in a paraphrase here but I I think the general question was what did I mean exactly when I said 128 bit data path versus it was actually five 12-bit vector register length so I'll just elaborate on that if that was your question yeah so so when I say 128 bit data path I'm effectively telling you that it can it can basically do vector operations at 128 bits per cycle to complete a full 512 bit vector which is actually the the length of the the physical each physical vector in the vector register file it takes 4 cycles to to do that yes well there's so that the physical vector length is is determined in hardware but you can actually program in software what lengths of vectors you're actually operating on i Lexi you want to say that louder so everyone else can hear yes it's a CSR hey Sanjay I'm sorry how many registers in the in the vector extensions so the the vector extensions specification is for the basically it's 32 registers [Applause]