Forward Initial Data with airSlate SignNow

Forward initial data

now we will see more details of this pipelining one important detail I would like to discuss is you know about right backstage I did decode stage just recall in right backstage what we are doing generally in the write-back stage you will be writing the register right in the register file maybe your instruction is like this ad R 1 R 2 R 3 then here you will be writing R 1 correct that means you are adding R 2 and R 3 in the earlier stages then after that we will be storing the result in R 1 correct so at the same time if you see there is a decode stage see the scenario entire scenario okay so sometimes it is possible that right backstage and decode stage will happen in the same clock cycle so what happens in vs. problem there are two independent circuitry right yeah though it is you know they are not actually exactly independent circuits the reason right backstage is accessing register file right it is writing something in to register but in the decode stage we are reading the registers correct example let say you have an instruction at r3 r1 r2 then in the decode stage you will be reading r1 which is currently your being written written right that means someone is writing into r1 and you want to read it if edit and both things happens then unexpected results come right so that is why what I would like to say is there should be one systematic order so always you can assume like this so this is your clock cycle a particular clock cycle and remember one thing every generally we design our pipeline in such a way that every stage can be completed in one clock cycle okay let us say this is you know a clock cycle and this is a duration now I can say that this is the first half this is the second half so your circuit generally will be designed such a way that especially when this kind of things then writing with what I can do is in the first half then I will try to I design my circuit such a that the in the first half writing will be done because that should be done first right second at the same time to not to collide with this right by stage in the latest half that means in the second half we will be reading okay so if you do that see this picture clearly explains you in the same clock cycle in the first half I will be rewriting and in the second half I will be reading so that the data which is written by this right backstage will be taken there will not be any problem but Sir why don't you do like this how in the decode stage in the first half you read in the write back stage in the second half you...