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we're now moving to the last paper of the session heterogeneous multiprocessor coherent interconnect Chi Chi Rica will be presenting she's she's not graduating or looking for a job she's been with ti since 2004 and she's leading the multi-core coherent interconnects platform steam where she's worked on shared memory and interconnect architecture and design for arm and DSP platforms for somebody to come to my team okay so I want to stress that we don't have the monopoly of using this world heterogeneous multi-core multiprocessor and coherence because it looks like there's a lot of familiar and traditional way that goes a long way beyond what we use word so over the entire presentation I'd like to actually represent what's the industry or on the chip level built building the trip process how we use this words and how we solve the problem on the on the silicon do I have all right okay so I want to start by introducing t.i Keystone to Architecture so this is the background that we are putting our interconnect so that's that's a new architecture that we have been actually relatively new not not very new if you google Keystone 2ti Keystone - you'll find a list of devices that is already on the on the market and mimic is the backbone of the entire Keystone to architecture to be able to put multi-core arm and DSP and potentially other processors to make this higher the heterogeneous platform work we have a lot of tricks putting in our interconnected to make every everyone you know every process process in their own speed and also we're the first one who actually runs at the CPU clock rate and the the crossbar is tricky by able to enable the parallel parallel compute and provide a simple use case use model for the force of software guys right so we are we're able to build the crossbar with the clock rate speed so that's why we're choosing this architecture I'm also going to introduce how we are putting this heterogeneous processes together on the same platform instead of putting different interconnects and then connected the interconnects together we actually puts the the cores are the same interconnect and they are actually can talk with each other share the same memory on chip and off chip and also go through the platform and talk with the SOC level slaves various management is very important for the shared shared resources we have multiple ways to adjust one more important thing as we know that our May 15 provides the coherence feature and our interconnect supports this coherent feature so then the i/o the peripherals the DMA can share data with arm without using any software currents ways for W you have to flush the cache here the hardware takes care of it so you don't need to do manually flush the flush the cache memory set protection address translation is to address the multiple course arm supports 40 bits address our traditional DSP and and system masters only can address to 32 bit so ms make steps in sorry will make you represent multi core shared memory controller starts in to do this translation aliasing and virtualization to make different course work on the same platform see all the available address space the last one is the MS mix scaling so from the previous slides we can see that people are willing or really desire to have more cores on the ship so how do we address that you cannot just put tons of chips on cores on the chip without paying any penalties right so we have certain ways to adjust that requirement so this is a very busy one the Keystone to is a platform that enables multi-core arm multi-core DSP or multi-core arm plus DSP platform so we deliver the highest performance at the lowest power levels to be able to give up to five point six gigahertz of arm so the calculation here is that one arm cluster has four cores inside each one of them running we enabled them running at one point six gigahertz so that's one point four times one point four that's five point six and also we enable eight DSPs on the on the trip each one running at one point three here we're using a marketing slice that is lower down a little bit to make it one point two but so their frequency is slightly different so you can see that form is make two to both support them then one of them has to have a a sickness bridge and I'm going to talk about that that bridging optimal for for embedded applications like cloud computing media processing high performance compute transcoding all of that is because we have two different processors on the on the chip they can share they so you can run a one for example the networking case you can run l1 l2 level in DSP and l3 and arm and then arm can can scheduling the tasks and you spit into different DSPs and so you can do a load balancing and task migrations easily and Keystone to Architecture also is the first TI platform that offers the standard quad arm cortex a15 combined with with the the TI TMS c6x acts high-performance new HP solutions so you can run with this embedded infrastructure to actually running closer to a general purpose processor ms make multi-core shared memory controller is the one that i'm going to talk today and it is the hierarchy the hydrogenous processor compute cluster platform so the roadmap wise some of the devices is already out so the three pass here the red one is the highest performance we make them running highest frequency biggest in numbers of course and the the most condensed compute and so for example the first one we have eight DSP course and for one mac bed of ram in the first generation of mimic they a middle range of that one we put 48 speakers and two Meg of as from in in the system and then you can even lower down to the most cost sensitive the are the lowest performance but high is the highest efficiency because of the power is also lowered you can have two DSPs and to my great effort that's from I'm mainly going to focus on miss make to because miss make one is the one that has the multi DSP core and miss make one the generation puts in the arm on in the picture and supports the coherence and all those fun features but keep in mind that this is the in the mimic roadmap we have been designed in the way that always consider the orbit ears of the devices on this platform so we enables the configurability is choose to support high performance middle range and low performance and high efficiency this is the overall crossbar topology on the on the left side you can see I can't stand work SoC we have the processor interface which is the TI c 6x and each one each interface has 256 bit bus and they're running at one point three gigahertz same as the Sigma the CPU frequency are may 15 has four cores in there so if you are familiar with their protocol they have they have a readwrite interface and then they provide a snoop interface so that is four supports the coherence in this make to be able to address the number line blocking problem we actually redistributed this traffic into non blocking traffic and blocking traffic so imagine if they have a request that that come into the shared memory controller and triggers the coherent the this triggers to snoop for that arm has mimicked has to to poke the core then the core has to deal with this the snooping coming back to the to mimic while there's another traffic another request right behind it also requesting the same one then you would have a a blocking issue so to avoid this this blocking percent potential blocking inside the crossbar interconnected at that we have we split to the traffic into you put all your snoop requests and all the cache maintenance on one channel which we named that is non blocking and all the regular traffic and that initiating the snoop the blocking channel so we guarantee that non blocking channel never get blocked throughout the entire mimic system so the the this potential issue that one you support to the coherency won't won't be a issue in our system so you can see that's why we have a we have three channels in there for for the arm at the the right hand the left hand corner there just the two to provide a snoop response and the other two ace channels for forearm and we also provide SOC slave interfaces there's there are two of them one dedicated for the chip from the other dedicated for the off chip as run so they don't blocking each other either and on the internally on chip SRAM we have eight parallel banks so every single master can access one bank at the cycle so okay how do we do the heterogeneous the processor connection this is the DSP only so you can look at this as SMS make one so we have shared run banks in parallel and just a a concept here for CC six acts with a XM c stands for external memory controller it has a prefetcher it has a reordering buffer inside and it does a clock conversion before in the first generation because we're running at clock - clock by two cpu clock by two frequency and then in with m'q - we did that so what happened is that the ego has a ax i - TI SOC bridge and this bridge is is used for asynchronous crossing so the core can the ego can run at one point or arm a 15 can run at 1.4 and mimic still runs the same frequency as the DSP and the whole system so what is inside the bridge so the left side is Miss maquon right side is a equivalency of the bridging inside ms make two so on the top we have the a-15 core and in between that's the bridge what the bridge does is the conversion bus conversion freak protocol conversion and we order in buffer so in the the color is different you can see between left and right because the clock timing pardoning actually does change and and from the from the arm side we have the snoop response and then we have the normal channel and the min smith side we have will make it non blocking channel blocking channel and widen the bus from 128 from 128 to 256 so therefore we can address the full bandwidth along with the rest of the system so bandwidth management side we have the so this is the signature architect arbitration inside mimic that we're doing it's called a multi-level user program or independent arbiter so in the in this diagram you can see there's three blocks there we have a request to party selection static priority and then a fair share so when the requests coming in they they bring in a priority number that's a three but encoded priority number system level you can user can control it and we respect that priority level and do the arbitration there but if you're on the same priority level then we're triggered this fair share selection and the fair share selection actually remembers the history when you are winning or losing and give a bomb that counter will not have a infinite counter that you know and silicon we cannot implement so there is a trick there and then if that still come up with ties then we do with a static priority and there's a a box down there saying skirving so in the ram bank we we have a ECC support the ECC actually has a background scrubbing it reads the data periodically and then corrected and then run it back and that guy needs some atomic read-modify-write so you cannot disturb it if if scrubber is winning the arbitration then it's it gets the banks for multiple cycles that it needs and then the fair share winner will take what takes the control okay so level one pretty much cover that what is what is not is this starvation bound so we still could have after all this arbitration some real-time requester could still be hunger so what we do is we we put in a memory map register so then the user can control this traffic to be to be bounded in a certain starvation balance if the threshold is reached then the request is going to be bumped all the way to the highest priority overall and then it will arbitrate among all the highest priority guys and and get a much better chance to one second layer is this fair share so this table is kind of tell you how we how we do this in with a little trick cycle number one compete masters ABCD they all have the same status let's say they are on the same priority candidates theorem and then you just use that fixed priority and and pick a is the winner then what the counter do the counter will say okay I see three three other competitors beaten by you so you are going to get your history count as no as minus three and everybody else get a plus one so and you can see the total credit if you plus add them together minus three plus one plus one plus one you got zero so this is a counter bound our count our counter will never go beyond minus three plus and to the plus three so this is this is how we are able to implement it in on the silicon without putting a maximum bound or a minimum bound here so the second cycle I've gone BCD is going to be the comparators with each other be is picking and then B has two other competitors so then he gets plus 1 minus 2 then his number goes down to minus 1 but we still maintain the credit total credit as zeros so such and such as psycho three and four and then here we are we built a compact competition history so from here on you can actually the number is showing how many times you want how many times your loss and then if there's a coming in again then you can you can see that a is not in the one and the third cycle and four cycle until it waits for its counter to be built up for him to be to be eligible okay so another trick that we're doing for the header fly head of line blocking is called escalation priority escalation so here is also a time line diagram for at the first number one diagram we can see CPU and CPU zero and CPU one has two two pipes so this represents the the in-flight request and the numbers is their priorities so you can see the CPU zero sends a whole bunch of priority number two which considered higher priority than priority number four for the CPU one so CPU one keep losing the arbitration because there's even a lower priority but it has a it did a contact switch and it goes to a critical task now and the priority number bumped up to one but he has a whole bunch of backlog of backlog of the number four priority that couldn't win that recursion therefore stop him from going pushing forward so what we're doing is okay I see a 1 in the queue so everybody else in front of this guy in the for the same core will temporarily assume number-one priority therefore it can 1 over number zero and then in the third cycle this this queue get drained and the critical tasks get pushed through so and then we also have if we remember the xmc external memory controller has a prefetcher it's a hardware prefetcher and we also have a squashing mechanism that if your prefetch is behaved your request you're not prefetching your post fetching then we just squash them and to let it go away because it's not demanding so we're not having any functional problems okay I will go Harris so if we have multiple cache in the system the coherence is the is the concern so two rules to follow one is at any given time all the caches are the components that share the data should see the same data if they're in the shared space second if somebody is modifying the data then or multiple ones are modifying the data then everybody that partition all the components that partition in the sharing should see the data change in the same order so what arm does is that they are forcing when somebody is trying to modify the data that shared with the other components then this guy will be guaranteed to be the only one that modify the data so what you do is you send a really unique to to the interconnect and then the interconnect to snoop everybody who has there therefore they don't have nobody else accepted this guy has the data and then he can modify it safely and then if somebody else that sharing the data wants it then it will miss his cache and go requested from the through the interconnect International out of the the modified core and give and and also make the data being shared among the multiple components so that's the the basic idea with the with the hardware coherence we we can avoid the software coherence solution that require manual cash flashing software into inter processing synchronization that's very time-consuming and error-prone so here I'm trying to show animation let's go quickly here ms make is sitting in between coherent CC represent coherence controller and the the little array there is a ram bank and DMA and a a 15 are supposed to sharing the data and there's a piece of block there a purple block inside a 15 represents that the data is modified at this block so okay if if ting is DMA now issues share read to the address a and let's make O'Hara's controller get through it gets the information and then issues a snoop for a 15 to ask for the for this block and then a 15 respond with the with the data that is updated to the current controller and then with make rather data into the shirt as from space and then given to to DMA so by doing this we are we're doing a spec spell ik speculative reading at the endpoint memory to allow the snoop latency and endpoint read latency to you over up so that way we improve the performance you won't see a difference if the data is shared it will be just read it through from the from the endpoint slave but if it is modified yeah we have to wait for the smooth to come back but the the memory will be updated simultaneously so what what happened if if DMA trying to write so if the DMA issue is read to the to the block a again and again the starting with the a-15 has that block modified so we assume that the DMA doesn't have a cache in there so that's a common thing and then rhythmic will issue a snoop back to the to a 15 at the same time it will write the data into the into the RAM bank and also remembers which which bytes or strobes are modified by DMA so it could be not a fall I write it writes the few few bytes so those bytes will be remembered in the in the RAM so I know that DMA writes the latest for those for those bytes but arm has old some new bytes for you know in their in their cache of the other ones so then when we get this snooped back then into the give the updated data that a 15 updates now we merge them together so so mimic will mask the stale bytes that is being updated by DMA and not updating those bytes and only updated the a 15 modified bytes so then you don't have to save what DMA has right what our arm has right numbers them together so then we save the we save the hardware to have a write buffer to save one of the masters writes and then merge with the second one and then right into you know the third step to do it we are allowing everybody to go through no blocking as far as I remember what you are the first one on the second one then when we make sure the functionality and data is always consistent this way okay this is a very busy one I think everybody read it from the paper it's very clearly stated how it works because it's a combination of the other examples the read write and and write and read again so okay memory protection this is what I mentioned before for for every masters to be able to see the entire memory space well because we're supporting 64-bit address space okay this is our dye photo if you can see that in the in the Army's armors here and DSPs are the DSP cords are here with me kids in the middle all these little blocks on the side are the red banks so we are in the with this problem we we we can reach achieve 1.3 googors at 25 28 nanometer process scanning oh you can put 4ms McCluster z' together and hook up with the system-on-chip infra infrastructure to be able to support four times of the core numbers so eight times for DSP and four times for arm oh and on the same device okay that's pretty much it