Integrate Heterogenous Signature with airSlate SignNow

Integrate heterogenous signature

please welcome jawad nozrala jawad is a chip designer with expertise in chiplets microprocessors hardware software co-design and sturdies previously jawad was the co-founder and cto z glue inc which is a silicon based uh silicon valley-based chiplet startup had set the direction of chiplet technology and developed a number of heterogeneous integrated circuits jawad is now working on his next adventure palo alto electron uh jawad has been very active with the odsa work group within ocp uh to help catalyze uh the triplet ecosystem before z glue jawad has held leadership positions both at intel samsung sun microsystems and transmitta android holds a phd degree in electrical engineering from stanford university so please welcome jawad hey great thank you so much abraham uh for the invitation so we had some great thoughts so far that makes my life easier i will primarily focus on system level aspects and some high level view of testability of these multi-chaplet or multi-chip implementations so my talk will be in in three sections but i'm going to skip the first one mostly because i'll just dive directly into the testing related aspects and one thing you will notice that i have this this terminology called system level test that's a little bit different than commonly understood so when i refer to system level tests it really means some kind of a structural test and some basic functionality combined and i'll finish it off with a chiplet-based example based on some of the work that we had done at z2 so i'll make a couple of points though last time i presented a design related talk so if you are interested in some of this you can look at the previous method presentation that i did but here i'm putting a five different chiplet design styles from a design perspective that we have various reasons or decision points why we go with one versus the other but one thing i did here is i listed out the classes of tests that would be needed for successful production of these systems and you will notice we need pretty much everything like all the way to final slt and even you know we need to think about quality and reliability my previous experience has been with active interposer type of 3d stacking so some of the things that i talk about are directly applicable to 2.5 d and maybe even to copper to copper hybrid bonding that's kind of like an upcoming technology so uh you can look at my slides on the flow of uh chipmunk-based integration but this is the first one that i want to mention here it's relevant so this is my view of how the components move through a manufacturing line and then what are the important ops and test considerations so on the left side you see a bunch of components some chiplets that might be interposer wafers and they definitely will be substrate panels all of that has...