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it's hard to miss the growing popularity of flash technology these days from the flash chips in our in our cell phones and our tablets all the way to the ssds for our laptops and in our server centers and largely we have to thank for this the growing bit density manufacturers have provided which help bring down the costs and increase the density in our devices unfortunately with this growing density the average and worst case performance is also in dramatic decline but on the bright side the best case performance still exists in our high-density flash devices so in this work we extend existing algorithms to manage flash technology chips in order to tap into this best case performance without hurting the wear out of the flash device or decreasing the device's capacity therefore we provide both the speed of the hair while providing the endurance of the tortoise i've done this work as my final paper for my phd and i'd like to thank my advisor my phd advisor stephen swanson at uc san diego and my mentor john davis from microsoft research without them i wouldn't have been able to do all this so before we delve into the details of our design let's start out with a brief look at the current state of flash management the flash community has fairly well understood basics of how to manage this very idiosyncratic idiosyncratic technology we're able to handle both wear leveling and this large block eraser requirement that we'll see a bit later through a combination of address remapping and log structured rights to the actual flash technology this is brought to our fingertips the low power high performance and ruggedness and small form factor we've come to expect from our flash technology it's helped improve our current technology and it's also enabled brand new application realms this is largely because as i mentioned the growing density of our flash technology so as time has progressed flash manufacturers have increased density through typical transistor scaling but also through adding additional bits to each memory element in the technology so when we started out we had single bit technology or restore only a single bit in each memory cell and we've increased this up to three bits per cell on the market today and in fact manufacturers have demonstrated up to six bits per cell as recently as this spring so we're increasing our density but with this comes changes in performance as well here we have the right latency in milliseconds of these three different technologies and as you can see it's dramatically increasing this right latency is going up quite a bit if we delve into these average numbers a little bit more we see a huge variation as we get into this multi-bit technology in particular the worst case performance increase the worst case performance declines even further the latency goes up but at the same time the best case performance remains roughly unchanged...