Recover Countersignature Time with airSlate SignNow

Recover countersignature time

Hello, and welcome to TI Precision Labs. In this module, we're going to discuss the clock and data recovery function, or CDR, used in retimer products. Retimers are a key building block in communication systems involving high speed data transmission. The use of CDRs provides improved clock and data synchronization and also reduces timing uncertainty. In addition, CDRs are valuable as a means of jitter mitigation for a variety of applications. Let's talk about the role Clock and Data Recovery, or CDR, retimers play in real systems. The example shown here is an enterprise switch such as those used in wired local area networks. As data signals are transmitted from one ASIC to another, jitter may arise from different sources. Jitter sources in a system include the insertion loss from the board traces, signal reflections at the connector interfaces, and crosstalk noise from the adjacent signals. Jitter acts as a bottleneck to system speed and performance, limiting the link reach and achievable bit error rate. A system such as this enterprise switch may use multiple CDRs to restore signal integrity at different points along the data path. Systems typically target performance to industry standards at each of these single points. Retimers are often required to meet those specifications. What function do CDRs perform in retimers? The retimer uses its CDR to sense the input data and produce a periodic and synchronized clock. This clock, recovered from the data, is then used by a sampler decision circuit. The sampler outputs a 1 or a 0, depending on its input voltage level, and its sampling of the input data is clocked by the CDR. This retiming function using a clean recovered clock allows the output to reproduce the input data but with much less jitter. The retimer thus allows the system to reset the jitter budget for a given data link. To illustrate the benefit of CDR function, let's examine the output of a 10 gigabits per second retimer when its CDR is enabled versus bypassed. The output I diagrams of the retimer shown were measured using a high speed sampling scope. The retimer test point used is the component edge, defined as a measurement taken for a short distance from its output pins. The total jitter values correspond to an error probability level of one! 1e to the negative 12. As evident when comparing the two retimer output I diagrams, the use of the CDR reduced to the total jitter by a whopping 45%. Let's examine how a system developer may determine what retimer has the best CDR for their application. Shown here is a networking system where two ASICs communicate over a backplane channel. The backplane will usually have very long PCB traces, thus the signal will be subject to large insertion loss, resulting in high jitter. In addition, launching the signal across backplane connectors will bring with it some jitter from reflections as well as crosstalk noise. A good retimer is able to handle a very jitter-stressed input signal,...