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of it Evanson who's the CTO of embedded for Xilinx thank you so good morning so today I'm going to talk about heterogenous embedded systems so let's dive into it so this is I'm coming from stylings we're doing these associate are feeling massively hetra dinos so this is the next generation we're going to come out with and as you can see that lots of stuff is a little bit hard to read here but there are multiple CPU calsters there there's a 72s few are those typically people run Linux on that let's say we have our five so what we call the RPS real-time process units typically people run maybe something like these to be safety certified maybe it's real time they need to have a faster response time for external stimuli and so on we have on the left side we have AI engines so machine learning is coming all over the place right so basically DSP and IANS they can do multiply accelerate accumulate really really fast but also being able to to place and route the different data streams both through the math Indians the AI DSPs and to the FPGA fabric that are going to talk about right so it's not only the compute but it's also how do you route the traffic through all these things how do you have different levels of hierarchies and so on so and then in the middle there we have the more traditional FPGA or fabric or programmable logic as we also call it which is basically hardware that you can reconfigure out in the field you can reprogram the hardware basically all right so you have a device like this from a software point of view lots of issues coming up it's not one homogeneous system where you can run applications in the same way all over the place so I'm going to talk a little bit about the issues that are coming out do this and also some of the solutions that we working on to to fix those problems we're at first couple of words on FPGA is I think last year has a similar slide here but just really a quick recap on an FPGA year so in FPGA is one of those things that's different to whoever you ask because they can be used in so many different ways depending on on how we program it right so in the everyday you have something called the programmable logic the look-up tables so you imagine that those are the places where you can put in your nor gate your NAND gates at the really low level you can program your hallway right yeah but over the years we have added lots of more hardened blocks for example memory everyone needs to use memory it's very very expensive if you use those look-up tables and then and and or gates to create the memory so instead what you do is that we have multiple types of memory and there we have something called block Rams that multiple read and write ports to it as you can get really fast access to it we have something called al-karim this is a little bit bigger SRAM in there and so on so forth right yeah we also have hardened DSP blocks they are different than the DSP engines we're now introducing so these are fixed point multiply to emulate store put all over the day after day so that you have memory you have lookup tables around it so you can create this really interesting data paths whether it's video networking or what-have-you so the use cases for this some people they use the F it is just as glue logic you have a funky bus coming in and you need to convert some things into something that your CPU can read for example so a lot of people are using it just for global logic and maybe that's some of our smaller parts some people are using these two to really do massively parallel compute like you have an internal signal coming in at the base station and you need to do a lot of parallel processing on that before you can eventually translate tcp/ip packet right yeah some people are using our really big FPGA is for emulation you're designing a new ASIC and affiliation really good at a decent clock rates you can actually simulate your design and these are these really big chips and maybe have a bunch of those on the board and then a multiple of those ports and you can simulate a big big system very that at you know several hundred megahertz clock speed so how do you program this stuff well the easiest way for software guy is that if someone else already wrote the accelerator that you don't use and you just use a library but if you're not that lucky then either you can go in and program in RTL code so over there's this hardware design languages like VHDL and very long or something that we've been bringing out the last few years that at higher levels your program in C C++ OpenCL and then we translate that to state machines is basically running in the FPGA this is especially powerful for things like when you do matrix multiplication right if you have a loop and then you can unroll that loop so you do 100 computation at the same time so every clock cycle you do 100 iterations of the loop for example right so if you write your code in the right way you can get a really parallel execution from it so that's the everyday it it's really fantastic in the sense I can do a lot of really specialized things and you can change that on the fly some people are putting FPGAs in the devices just as an insurance policy they know that they probably didn't get their design 100% correct so they want to be able to update that in the field later on so that sort of the global logic combined whether it's some other accelerated capabilities there alright so why do we see these heterogeneous systems coming up right there I think there's two main reasons and this are not going to everyone knows this that the old idea of using a CPU and then every year it will be faster it never used lower power and so on so forth those days are long gone right we all know that so instead we started to do multi-core but then we realized that it's hard to manage you can't just scale and have more and more cores of the same type so now really the solutions becoming using specialized accelerators specialized engines for the task at hand so that's really efficient from a hardware point of view but it can scripts up things from a software point of view because all these are programmed a little bit different you have to manage them and a lot of of those kind of software issues but we really have to go there because the workloads are continuing to go up especially now when you have things like machine learning which is really compute intensive so that's one one of the reasons another reason it's really more about integration so so the device is out there this is an industrial device maybe it used to be separate different boards maybe have one PLC board doing sort of running or app if you will connect into the server or nowadays to the cloud and you have maybe a control card in this case controlling a motor so that needs to be real-time something happens with motor and you need to get those signals back and react really really quickly so you can't have your processor suddenly wrong and do something else you need to be on top of things so that's that's the the short latency and deterministic behavior that you need from those kind of systems you might have another board that had handles safety issues a lot of safety issues are coming in lots of different industries opinion industrial automotive of course it's coming with two six two six two standard and safe this all about how do you protect the world from from the device you know you don't want to have code that solid doesn't work anymore so your brakes is not working for example and that's very expensive code it takes a lot of money to save the certified system so you don't necessarily want to have all your code safety certified because it's it gets way too expensive all right so now we have these three boards you want to save money you want to save power you put it all in one SOC but you still need to have this separation between general-purpose real-time and safety create some issues so if we look at one of the current devices that we're going you to use this as an example going forward so this is the distinct MP so it has for a 53 s so that's the ApS application processing unit we have to cortex or fives again typically people use that for safety or real-time and so on we have a platform manager that's a hard and microblaze that's a CPU coming from micro from tilings we have the programmable logic the FPGA fabric so there you can put in what we call soft course so we have this micro blaze now also from arm we have a cortex M 1 and M 3 course so there's a soft course so you can put in many tens or hundreds depending on the size of the device of those in there as well you have all these different environments you get first of all all the environments for each and every one of these course but then also some of the course they have different execution levels so take 350 trees for example they have l0 where you run your user application typically you have the yield one where you have Linux and the kernels you have the hypervisor if you have one that's at the l2 and your three there you have the firmware and on top of that you also have the trusted environment trust zone actually might have a trusted execution environment there of T or something like that so you have all these different environments where you're going to write your code you don't necessarily know where the code will end up so how do you write code that you can then put in all these different places so that that gets kind of tricky especially since the operating environment is different Linux these days I would say 80% of our customers are more than that are using Linux typically on the on the a course but then they have companion operating systems or bare metal and those are open source like free or toasts or or safer but very often proprietary vendors there are lots of them out there from Wind River and green hills and so on so forth so again in that ecosystem we have to make it easier for people to be able to put these things together to write code once to configure these things so how can we simplify this instead of the ad-hoc having a shared memory and we all come up with our own way it's kind of fun to write that code right in the processor interrupt and initiate page or something like that but why should everyone have to do that over and over again so the things that that you have to tackle an or how do you configure these systems how much of the physical memory goes to this core in this environment versus this which device hangs to Linux versus to free autos for example right how do you lifecycle manage this how do you if you want to start up something a new application on another core and maybe it's crashes you'd want to be able to detect that you want to be able to restart that to do that you actually have to know what devices belongs there you have to idle those buses you have to maybe reset the devices there a lot of things that needs to happen why should that be ad hoc for for every device from silence or if it's from other silicon vendors as well right how do you share resources to have a graphical card or a GPU and maybe Linux is is dealing with that but you do want to do some graphics from from vxworks how do you do that how for all these different operating systems how can we make it easier for them to port in all these different environments from all these different vendors yeah so we have created something we call open amp to try to solve some of the of these of these problems so the open amp initiative something we started about four years ago and we're really trying to drive standards through open source we find that that's the fastest way to to get synergy is to have example code out there right so it's really all about EMPs as a symmetric multiprocessing we are both looking at the standardization and just using a term barrier in the liberal way here because we're not really writing big standard specs we're more documenting the protocols of reusing like what I owe what different flags means what and so on so let me know that we're backwards and forwards compatible we add new features right so open amp and then we have a cleanroom implementation of things that's already existing in open source things like remote i/o remote proc or P message so those are existing in the Linux kernel you can't just take that code first of all it's entangled with the rest of of Linux a little bit but also you can take that GPL code and put into a VxWorks or Makram or toss so we have written this cleanroom implementation of those and that also means that instead of always having Linux as the master we now can have a small Otto's as the master storing up Linux or you can have 2mc use running orthosis and not have Linux at all soken amp'd currently doing these things to lifecycle messaging and these things we have a low level abstraction layer that obstructs like memory and in the process interrupts and things like that to make it easier to port your your operating systems on the different environments in the group right now a bunch of companies or sales I links we have t.i we have SD micro we have Mentor embedded Qualcomm Wind River micro mr. Wan this bunch of people some people are actively contributing code as you should with open source projects and a lot more people are using it and there's a bunch of companies using it they're not active in there in the discussions as well yeah so this is something that that we are working actively something we're just starting to talk about is trying to attack the configuration issue how do you configure as I mentioned what memory goes where so that's a new concept that we call system device trees that we just started so this is just more informational and the the question here is that you have a bunch of hardware that describes the SOC and the board and then you have this different domains yeah maybe Linux domain maybe have a trusted environment maybe have an or toast or somehow we need to communicate the memory hierarchies the buses which physical memory goes here and there which devices goes where right silence our hardware engineers they like everything to be really really programmable so you can reprogram a lot of different things like a device where where will it hang on will the tank to the or fives or to something else but we need to specify those things in our programmable logic we can add new neat network interfaces a lot of new things there we have to express those things so you choose to express it with device trees but we need to expand device trees from just looking at one address space to multiple address spaces and their mental model of this is that you have a description on the whole system you have done some input files but saying that well for Linux I need this address space these CPUs I need this much memory I need these devices or from the system device tree and create a regular standard device tree as they exist today for the Linux environment do the same for the bare metal environment for the free autos environment and then we working with our partners and internally we are going over that we're using device trees for our bare metal for all three autos and and so on so we're trying to make this a little bit of an industry standard which it's very early on so we see how we can do that if we're successful you can also use this to verify later on when you integrate all these different parts you can verify that the different petitions are not using the same memory space for example under stay of supposed to do because when you have these systems it's really easy to screw up and you know just get one address a little bit wrong and then both systems are going to the hammer on the same device for example right so let's talk about hypervisors so we would be talking about this in P systems where we have different processor types but really a lot of our customers what they want to do is - oh you have four 853 is there I want to have an autozone that core and I want to have Linux on digit ofcourse and I was the safety certified maybe and things on another core well it's not that easier ITA 53 is a really bit more for an SMP system of course you can have a hypervisor on top of it so the use case is very very similar you typically pin the open system to a particular core so that's fine you can use open amp and the things that we have ported open amp to them so you can use that for for the messaging things like that in the future as we developed the system device trees that's perfect to use for hypervisors as well to allocate devices to the different partitions and the different domains in indocin speak there's one issue here which on the a53 and AC empty tubes and those kind of cortex a-class processors is that the the level 2 cache is shared so that means that if you have something that's very time critical you have a real-time partition that really needs to have a deterministic response time for something well then you have Linux running over here maybe Linux is doing some mem copy the big blocks but that will learn impact your real-time petition because the level 2 cache unless you can run from internal memory and very often you can do that we have several types of on chip memories and things of that or if you run within the level 1 cache then you're fine but if you have a little bit of a bigger application then you have a problem it's not deterministic anymore so we'll be working together with some partners on a solution called cache coloring so not coming into the details of cache coloring but at the very high level what you're doing is that since the physical memory each address is mapped to a particular cache line so you can imagine looking at your memory in these blocks let's put code called colors of them that's repeating all over but let's say that we allocate to the autos petition physical memory that corresponds to one of these colors that say green and then we make sure that when we allocates the physical memory to Linux we avoid the green ports then we know that Linux is not going to hit those cache lines so that's what cache coloring at the very high level you can look it up in and it's kind of interesting so we have been implementing that in a hypervisor the first one we implemented this is in the jailhouse hypervisor been working with the University of Modena to do this and the result is really really encouraging so you can pretty much do whatever you want on these other cores running Linux and so on and the real-time response time is very deterministic on the core where you need that using cache covering a little bit of a kludge and hopefully in future arm course you have better ways of doing that with impairment and things like that but we live in a really pragmatic world to help to fix these kind of issues right okay so we've been talking about this help to deal assistance with a lot of compute power you might ask well those guys are probably very expensive you know can I use them in my system well so Avenue to section now introducing the ultra 96 version - so this is alternate the six board came about a year ago I think and this is the second version of it second release it's a 2 $49 board and it has the same process that we've been talking about it's really good for things like artificial intelligence embedded video those kind of things all right and it also is designed to be of the 96 port form factor and that means that the 96 board code will run on it as well so you got that ecosystem over here as well yeah so that's going to be released in May and with that you get the board you get an SD card but you also get the license to our what we call the SD SOC tools where you can write your code in C C++ and it will translate that not only translate the code and put that into the FPGA but the rest of the code we'll do all the glue in between so you just call AC function and then we'll take over take care about the DMA transfers and all that stuff back and forth so that that will be available may the outer 96 first version is available today of course all right so we're talking about SOC home heterogeneous systems within one chip what about if you have multi chip solutions so what's the situation there and if the clicker works there we go so typically what you do then is that you have some kind of CPU cluster you talk over a bus like PCIe over to an accelerator right and that's well known way of doing things been working for for quite some time the programming paradigm there is really that you write the driver you set up some dmas you copy your data back and forth they have the accelerator working on it and get the data back and so on so the question is can we make this a little bit more similar to to this heterogeneous SOC course that we've been looking at before right and why would you do that well it's really because the accelerators are becoming much more more more smart they you want to program in a different way you want to have a shared memory for many use cases where the CPUs they populate the data there and then we can have an accelerator in parallel maybe doing search on that data or or manipulating smart memory whatever you have so suddenly you get this need for a Numa kind of like on memory so maybe the the access times are a little bit different but it should really look like one cache coherent memory block for the for the software on both sides then the programming model becomes much much easier so this is really what c6 is all about as it's really virtualized cache coherent accelerators it's based on top of the PCIe standards of things like discovery and all those things are compatible with that but you don't need to have the drivers to you program it more you do with with a more coupled system where where you have shared memory in between it which for a lot of use cases really really helps out all right so the c6 consortium I think this slide is a little bit dated it was 50 member I think it's more than 50 members now but it's really big consortium and the first devices coming out this year on the hardware side lots of people that then are supporting software stacks on top of it so this is really a new exciting way of doing accelerators they're connected to something else and the nice thing is that with the c6 standard you can also use so they have multiple dies that are connected really closely together and create those kind of systems as well all right that was my last slide time for a couple of questions sorry I think that we do anyone I think that was really fascinating and a great explanation for open EMP and also c6 anyone have a question there was a lot there know where everyone is mmm rinse coffee exactly alright so Tomas thank you so much for joining us and sharing that with us today we really appreciate it that's great