Scan Collector Ssn with airSlate SignNow

Scan collector ssn

hello my name is michael brown i work for advantest in germany and i will talk about how we work together with siemens tescent to accelerate scan tests with ssn and 1149.10 on the v93000 soc test platform if we look at the overall growth of a scan volume we pretty much see that the only way is up this is actually an sort of old graph from itrs which forecasts an exponential increase in the scan memory requirements it is very valid until today uh what we have seen over the years is a scan volume doubling every three years more or less on the tester just recently the pace is actually increasing so the volume growth is faster and as a consequence of that we must work on increasing the scan throughput on the ate to prevent an explosion of test time we've already seen customers going from seconds of test time to minutes and we have to work on faster access mechanisms to pump all the data to the device which is required to achieve the target defect coverage from an ate point of view we have actually three options to increase the scan throughput so from left left to right the first and most obvious one is actually to increase what is mostly being done today which is parallel access to gpio pins and a prominent example of this increase on well-known paths is actually the tessense streaming scan network ssn it's a time multiplexed parallel bus of variable widths has a speed range of 100 to 400 megabit runs through the entire device and delivers the scan test data to all the individual cores which are about to be tested in parallel inserting it in existing devices in existing designs which use tessent is a relatively organic dft change and right now as a result of that it has obviously a big momentum in the industry it's it's well supported by the eda tooling it works on the install tester base that's a very important thing and it does not come with special hsr requirements some of our customers have invented their own variants of such and such an access scheme so they they have in-house implementations of faster parallel buses with uh time up in multiplex questions but uh this is this is the the most obvious sort of lowest hanging food uh to get to a significantly uh higher scan throughput to increase ranges in the uh in the ballpark of something between 2x and 16x over uh a standard parallel scan bus running at the shift speed essentially which is typically 100 megahertz then in the middle there was an evolution of this scheme which is 1149.10 hsro so that is itself a high-speed seal access schemes where a larger parallel bus gets replaced with a smaller serial access scheme but uh the speed of the individual pins is much higher so we're talking lane speeds in the gigabit range somewhere between...