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Scan deponent calculated

[Music] hi I'm Rohit Kapoor I'm a distinguished engineer at cadence today I'm going to give you an introduction on scan compression let me start with describing scan design what you see in this picture out here is a design with three scan chains there three scan ins and three scan outs and you have three scan chains in this design which represent all the flip-flops of the design as designs have got larger the number of flip-flops has increased much more than the scan IO and these scan chains have got longer and longer so what does a test pattern look like in scan what we end up doing is we apply a stimulus which is a shift operation into the scan chains and then after that we apply a capture cycle and then we scan out the response the adjacent patterns are overlapped and hence the test time if you were to calculate it for a single pattern is the shift operation plus the capture cycle which is primarily the shift operation alone because it it's pretty much the length of the chain so if this chain length is about 100 then the shift time is about hundred cycles and the capture cycle represents about one cycle or two cycles so the test time is dependent on the scan chain length and of course multiplied by the number of patterns that you have for that test set so the more longer the shift length more the test time if you compute the data volume it's a similar calculation in this case the stimulus and the responses that are saved on the tester are also represented in this equation where it's multiplied by that amount of data again the data volume also increases as the chain length increases so this became a problem specially in the early 2000s and the test data volume and test application time had to be addressed because the test cost really went up in the early days of solving this test cost issue the one solution was presented was the low cost testers basically the 8ee equipment represented a huge expense which was the which dominated the test cost of a single chip however the low-cost testers did not solve the all the test problems of a single device and hence it was not a successful direction to take for solving the test cost problem logic BIST was a solution around the which was available in those days it was also known as a tester on chip it represented having zero data volume meaning you generate all the patterns on the chip itself but the patterns were all random and hence it took longer to test the device logic based flows also required X cleaning the design which was very difficult for or to do it for any average design so logic bist also was unsuccessful for those reasons finally the final solution which actually got adopted was scan compression I'm going to now...