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[Music] dear student welcome back to the DFT video in this video we are going to introduce one of the most important DFT technique the internal scan technique because again is such an important DFT technique so we have different skin available for different design for free flap based designs we have mock ste scanned proposed by Stanford in 1973 we also have clock scan proposed by NEC in 1968 for edge based design we have LSST proposed by ibn in 1977 these techniques will be introduced in our following videos in this video we will first talk about general concept about game the idea of scan is to connect internal three flaps or latches as a shift register so that we can control and observe the internal free flops or ledges in test mode please note that we still want to remain the original circuit function in normal mode the idea of scan was first proposed in 1970s by Stanford University and other companies scan remains one of the most important DFT technique for synchronous digital circuits the pattern to figures shows how we can insert a scan chain into a design on the left hand side this is design before scan insertion the yellow squirt represent none scan free frogs or latches after scan insertion we replace those none scam free flap into scam free frogs as you can see the orange squares are larger in area than the none scam free flowers and the second step is that we need to stitch those scam free frogs into a chain in this way we can scan in our test pattern and we can scale out testers pounds in test mode this procedure is called scan chain insertion or it is also known as TFT insertion or DFT synthesis in the design flow this light introduce the concept of scam free frogs or SFF please note that we will use free flap as an example in this video for let's paste design the concept of ten latches is very similar for scam free frog we have four important pins scan input pin si and the scan output pin as all these two pins are used to connect the scan chain as a shift register and then we also have data input pin di and data output pin tio these two pins are used to connect scam free flap from and to the logic please note that the open and so pin sometimes can be shared as a same team a skin free frog has two functions it can perform a shift or a capture a circuit with scan chain has two operation mode normal operation mode and the test operation mode in the normal mode scam free frog are configured to perform capture so they captured the response from the logic and they apply their response to the logic so this is exactly the same as the original circuit in test mode the skin free frog our first configured to perform ship operation so we can ship in our test pattern and then the skin flip-flop are configured to capture the response from the logic for one or a few cycles then we can configure the skin flip-flop to perform a shift out operation so that we can observe the values in the skin free fall now let's see an example and the left-hand side we have original circuit with none scam free fraps after scan insertion we replace these two free throws by scan tree frogs and we have scan chain insert it into this circuit now in no more operation mode the skin free flap is actually the same as none scam free file in this mode a scam free flap will capture data from the data input suppose that the skin free for one is initially one and the scam free flap - is initially zero and we apply a zero at the primary input so we can see that the output of n Kaede is 0 and this is also 0 so the output of all K is 0 after one o'clock the data would be captured in the scam free file so now scan free for one is zero and the scan free part 2 is also 0 this is exactly the same as the original circuit now in test mode suppose we want to detect a stuck-at 0 here so we would like to shift in our test pattern a scam free flap our first configure to perform a shift operation because we want to activate this fall so we will need a one at the primary input and also we will need one ad scan prefab number one also we want to propagate this full effect through the or gate so the site info here must be 0 so we want scam free flop number 2 to be 0 so we can shift in a test pattern 1 0 into this scansion this figure shows the free state after two cycles of ship and then we can have a 1 slash 0 at the output of the or K and then we come figure the scam free flop as capture so we can capture response into the scam free flop 1 slash 0 which means that for the good circuit the value should be 1 and 40 circuit the value is 0 and then we can perform a shift out operation of 2 cycles at the output here we can observe 1 0 at the second cycle in this way we can detect this stuck at 0 4 in test mode please know that this fault was originally untestable in normal mode do you know why please think about it now it's time for you to work on the quiz suppose we want to detect a stuck-at 1 fault here please pause the video and the few in the question mark ok have you finished if we want to activate this fall we will need a 0 here so this flip-flop we need a 0 to propagate this through the olcay we also need a 0 here so we can have either a 0 here or a 0 at primary input either one of them fine and then after a capture we can capture the response here which is 0/1 for good circuit this flip-flop should be 0 for 40 circuit this flip-flop is 1 and this flip-flop is supposed to be 0 now we shift out the contents and we are able to observe 0/1 at the end of the second cycle have you get it correctly as we can see from the previous example scan can actually turn the sequential circuit into a combinational circuit in the test mode because the free flops are fully scannable so we can fully control the output of the free flap we can also fully observe the input of the flip-flop so actually we can ignore this free flux in test mode so what ATPG really sees is only a combinational circuit model where PIR primary input of the original circuit and the PIO are the primary outputs of the or neutral circuit and the scan free flap data output now becomes pseudo primary input for this combinational circuit model because they are fully controllable also scan free from data input now becomes pseudo primary output of this circuit because they are fully observable so for ATPG we only work on this combinational circuit model this is a very good news scam makes a TPG a lot more easier now it's time for you to work on a quiz suppose we insert the scan chain into the circuit so we can actually remove them in the ATPG please tell me which of the pins primary employment output pseudo primary input and pseudo primary output question number 2 if we want to detect this stuck-at 0 fault what are the values of this question mark please pause the video and work on this quiz okay this one is easy right primary input is 8 and primary output is z they are the same as the original sequential circuit for scam free flop number one it's called found two pseudo primary input number one for scam freeform number 2 the output is pseudo primary input number 2 to detect this stuck-at 0 fault we require one here and one here so PPI number one must be one and premium poll must be one to publicize this fault we need a zero here so PPI number two is zero at PPO number two we can now observe 1/0 here in this way we can detect the phone so now we only work on this combinational circuit motto which is much more easier than sequential circuit scan is such a good powerful test technique but it does not come without cost the advantage of scan is that we can have systematic TFT it's not a lab TFT so we have many automatic tools to help us to insert scan chain automatically also it makes ATPG easier so that the run times faster and the for coverage is higher if you want to know more details please see video 11.4 with scan chain we can do 2nd debugging or diagnosis more easily silicon diagnosis means that after manufactured some prototype chips we can use scan chain to help us to debug if there is anything wrong with the prototype chip we can shift out the contents in the frame frog and observe the values so this is very good for debugging but there are some cost associated with scan first of all we need more area for design with scan inserted because the scan free flap is larger and we need some area for routing of the scan chain typically five to ten percent of area overhead is acceptable second we have performance overhead because a scan tree frog has longer set up time and hold time so performance of the chip can be degraded after scan insertion and also we need to pate pin overhead we have more pins such as scan impulse can output scanning multiple pins skin cracks pins etc please see the other two videos for details also a circuit with scan chain in 30 would cause more power and we also need extra design efforts to insert a scan chain and a verified scan chain please see these two videos for more details now it's time for quiz suppose we insert a scan chain into this circuit and replace those numbers can be brought into scheme free-falls given this gate area table please calculate the area overhead of the scan DFT the area overhead is defined as the incremental area over the original area before DFT now please pause the video and calculate the overhead okay are you finished in the denominator the original area of the circuit is one or gate and 2nk and two nuns can't reform so that would be nineteen after TFT we have to scan free from that will be twenty one so the area overhead is two over 90 which is approximately ten point five percent in summary scan is one of the most popular DFT technique for digital VLSI and scam free has four important pins skin inputs can output data input data output a circuit work skin has to operation mode in normal mode skin free fraud captured data from the logic in test mode we first shifting the test pattern capture the response from the logic and shift out the contents in the game chain skin makes ATPG much more easier but the cost is area overhead and the performance every year overhead and many other more at the end of this video I would like to ask you questions we mentioned that this fall was actually untestable in normal mode please explain why and the question number two since is untestable why do we care about producing about this two questions thank you [Music] [Music]