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Scan esign test

hello friends today we are going to see about scan based esteem scan based testing is one of the structural approach which is used to test a VLSI circuit usually these will be used in complex circuits and the circuits which have a two layer or a three layer design because accessing the internal nodes become very very tough so what we are going to do is we are going to implement a Sumanth testing circuit inside our IC by doing this it will cover some area but we will have a better performance since the internal nodes are not accessible so in order to perform this circuit we require at least one node which should be accessible without that we cannot perform this test so here we have two modes of operation one is normal mode and another one is scan mode in normal mode the so acute serves their basic function that is they will do that basic task for which it is made and in scan mode they are connected to a series of flip-flop which will be traveling throughout the circuit here we have the block diagram of scan based testing you can see we have a multiplexer followed by a flip-flop so usually the flip-flop used is the D flip-flop and the scanned input is connected to the zeroth input of the flip-flop and one will be having the data input so this and selection signal is responsible for the inter operation whether we are going to perform a testing operation or whether we are going to perform a normal operation so these flip-flops are connected to the logic cloud and again for the second set of the operations we have another set of flip-flop so now what I am going to do is I am going to perform a scan operation so I am going to set my scan input to 0 that is the scan selection input to 0 so when I give a scan selection in put equal to 0 the scan input 0 input is selected there is 0 the input of the maxis selector and it is given to the flip flop so in the flip flop we'll be having a clock signal so based on this clock signals rate our data will be shifted and finally we'll be having a scan output so this is our observation point and in this observation point we will be observing the output for each and every test pattern so based on this observation points output will verify whether the circuit is working properly or not here we have an example for a circuit with two logic loads so as the logic clouds increases the number of flip-flop also increases so then we have a more number of logic cloud the operation really becomes complex and it will be time-consuming this is one of the major drawback of scan based design especially in RAM circuits where we have so much number of logic blocks the timing will become very very high so in order to overcome this what we are going to do is we are going to use the parallel base design in parallel scan we are going to split our complex circuit into smaller block and we are going to rearrange in a form of matrix so this matrix is controlled by using the row signal and column signal so we have a row signal N and a column signal M based on these two signals we will be giving input to our flip-flops whether we have a testing operation or normal modes of operation so while testing the data are shifted using the data signal and this write signal is used to when we have a normal mode of operation that's for today and in next video we'll be seeing about the built in self-test thank you