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Scan heir ssn

in this presentation we will describe the new high-speed approaches to scan testing with streamless scan networks and the ieee 1149.10 standard and how the partnership between siemens tescent and teradyne is focused to enable your success first let's look at the motivations for new approaches to scan testing quality continues to be the primary factor which relates to the continued increase in test data volume as advanced process nodes reach 3 nanometers and below the defectivity remains the key challenge yield learning in the initial phases is still important where higher coverage and large magnitude of scan failed data drives more test data additionally more fault models are being added such as cell air and others to target the remaining hard to reach defects this also contributes to higher test data volume without increasing the scan data bandwidth the test time has become an increasing factor this becomes worse as the number of external pins available for scan are limited and in many cases being reduced a solution is needed to provide a significant increase in scan bandwidth finally device power supply transients during scan testing continue to increase in some cases up to a thousand amps or more with decreasing dc levels well below one volt the dynamic performance of the power supplies has a strong impact on the resulting yield additionally these high currents raise the risk of interface damage or device thermal runaway if not protected by the ate instruments to address these challenges the industry is adopting new dft approaches to scan such as ssn or streaming scanned networks and the ieee 1149.10 standard ssn itself provides significant improvements fundamentally by breaking the tight coupling of the external scan interface from a block scan chains ssn helps address the test time challenge in multiple ways the scan data more efficiently targets the circuit under test resulting in reduced test data volume the internal network can run faster as it serves multiple test blocks in a time multiplex manner which results in faster and pattern bursts typically up to two to four times faster the natural artifact of testing multiple blocks concurrently with this design can result in more dispersed power transients helping control the device power supply impact and not restricting the pattern rate and the on-chip compare option for multiple identical cores can allow a significant reduction in test patterns but possibly at the cost of fail result detail resolution ssn also helps with lower overall effort the scan patterns are block focused and can be reused across device variants the separate retargeting nature of the block focus pattern allow the test pattern packing to be optimized post tape out the 1149.10 standard layers on top of ssn providing additional benefits higher scan bandwidth can be achieved by using order magnitude faster external surges interfaces while also significantly reducing the number of pins it also provides the option to reuse existing certifies for the most significant test pin reduction overall this ensures low risk...