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Upload countersign calculated

let's look at timing checks in this module let's identify what the setup and hold checks imply how it affects the flops and how information is stored in the flops then we will identify how they are stored in the libraries for the sta tools to use a flop or flip flop or register as it is commonly known is one of the common storage elements and it is edge triggered if we look at the timing arcs in the flop you have the d to cue timing arc and then you also have the clock to queue timing arc one thing to remember is that in an edge-triggered flop the input data is propagated to the output only when the clock triggers the data to go from d to q output so all the timing information that is calculated is from that clock edge when you look at the timing calculations the clock to queue delay of the clock to queue timing arc is what is used in timing sta tools will use that clock to cue delay whenever you look at timing reports the delays are calculated from the clock edge so the important timing parameters in a flop are the clock to queue delay we also have setup and hold time requirements we'll talk about those in a second for the data to be safely stored inside a flop the data must be stable for it to trigger the saving of the data into the flop if the data is not stable and changes during the setup time the data is not stored in the flop if you look at the graphic below there is some slow logic and the data is going from q1 to d2 the data is being transferred from ff1 to ff2 if you look at the d2 signal the d2 signal is changing before the cycle 2 of the clock starts the new data is ready to be saved into ff2 at the rising edge of clock cycle 2. but the d2 signal just changed value right before the clock edge without meeting the setup time requirement therefore the data will not be stored into ff2 the reason for this is the slow logic obviously q1 and d2 are different signals and even though they have similar waveforms there is a delay between them the q1 signal takes some time through the slow logic to arrive at d2 q1 data from the previous cycle change before the cycle 2 begins because the rising edge for clock in cycle 1 triggered new data into ff1 thus changing q1 and now the new data is already at q1 the old data barely arrived at d2 and was not yet saved into the target flop ff2 before changing into the new data thus by not meeting the setup time of the flop it caused a setup violation therefore setup time can be defined as the duration of time that the input data must be stable...