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hi my name is Ethan Essen I'm a tme for Mentor Graphics and in this presentation you will see how you can use I J tag to edit and insert DFT for mixing all devices one of the tasks that the FTA engineers often need to do is add control and observation points to different IPS for example mixing devices with Tessa I J tag you can do this automatically you can also make IPS and your design I creepily sixteen eight seven compliant that's I J tag you can create invalidate the instrument connectivity language or I CL or ecole and the procedural description language or PDL files we can run tests to validate your IPS which means you can actually generate test benches and test patterns on the tester you can also create test setup procedures with it to properly set your design in a PPG or scan test mode basically tessin IJ tag provides automation that helps you save time and effort on these DFT related tasks and that way you can focus on more important things one of the main features of tested IJ tag is that you can use it to insert an ID tag network around your IP blocks for instance you can add scan Lux's test data registers and so on all scripting is tickled based you can typically invoke now Stickle procedures to straight from the tool for example if we take the PLL Illustrated here it's normally driven through parallel inputs the DFT engineer could therefore add TDR allowing you to shift in new values and then update them into the device this implies creating clock scanning and scan out and also the captures shift and update ports once the TDR is created mapping its actual bit values to the PLL inputs can be documented or not so what are the exact benefits that Tess and I J tag brings in this case firstly it's able to extract the an activity down to IP instantiated inside the design it starts from your IP block and it extracts the connectivity by tracing up another benefit is that you can take the lower level tests that were defined for that IP specifically and they can be retargeted those tests are completely regenerated taking into account that there is an access network between the IP and the top-level IPS that are IG that compatible are no longer constrained to use specific test interfaces the test pattern generation is also interface agnostic the tool basically figures how to get through the eye JTAG Network you can generate very log test benches for simulation or you can generate style wiggle in svf pattern formats for silicon tests over all this reduces the support and documentation burden that you need to come up with it puts the focus on the IP functionality itself not on the test access method that has been chosen to access this IP also the IP level IJ tag files are self documenting...